
Search the dblp DataBase
Subarnarekha Sinha:
[Publications]
[Author Rank by year]
[Coauthors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
 Subarnarekha Sinha, Robert K. Brayton
Implementation and use of SPFDs in optimizing Boolean networks. [Citation Graph (0, 0)][DBLP] ICCAD, 1998, pp:103110 [Conf]
 Subarnarekha Sinha, Andreas Kuehlmann, Robert K. Brayton
Sequential SPFDs. [Citation Graph (0, 0)][DBLP] ICCAD, 2001, pp:8490 [Conf]
 Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton
Topologically constrained logic synthesis. [Citation Graph (0, 0)][DBLP] ICCAD, 2002, pp:679686 [Conf]
 Subarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. SangiovanniVincentelli
Binary and MultiValued SPFDBased Wire Removal in PLA Networks. [Citation Graph (0, 0)][DBLP] ICCD, 2000, pp:494503 [Conf]
 Robert K. Brayton, M. Gao, JieHong Roland Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko, Subarnarekha Sinha, Tiziano Villa
Optimization of MultiValued MultiLevel Networks. [Citation Graph (0, 0)][DBLP] ISMVL, 2002, pp:1680 [Conf]
 Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton
Topologically Constrained Logic Synthesis. [Citation Graph (0, 0)][DBLP] IWLS, 2002, pp:1320 [Conf]
 Sunil P. Khatri, Subarnarekha Sinha, Robert K. Brayton, Alberto L. SangiovanniVincentelli
SPFDbased wire removal in standardcell and networkofPLA circuits. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:10201030 [Journal]
 Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata ChrzanowskaJeske
Using simulation and satisfiability to compute flexibilities in Boolean networks. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:743755 [Journal]
Automating Logic Rectification by Approximate SPFDs. [Citation Graph (, )][DBLP]
Search in 0.035secs, Finished in 0.035secs
